At-Speed Path Delay Test
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This research describes an approach to test metastability of flip-flops with help of multiple at-speed capture cycles during delay test. K longest paths per flip-flop test patterns are generated, such that a long path on one clock cycle feeds a long path on the next clock cycle, and so on. Traditional structural delay tests do not test whether time borrowing or stealing is working correctly, since only a single at-speed cycle is tested. To detect path delay faults for the multi-cycle paths, it is necessary to start a path at a register and end at a register while passing through another register, testing the longest paths between each pair of registers. This requires three or more at-speed cycles, rather than the two of traditional Launch on Capture test. This produces power supply noise closer to functional mode, and permits the testing of flip-flop metastability and time-borrowing latches, that cannot be tested by any other structural test technique. The path generation algorithm uses the circuit structure, and then the paths are sequentially justified using Boolean Satisfiability algorithms. The algorithm has been implemented in C++ on an Intel Core i7 machine. Experiments have been performed on various ISCAS benchmark circuits in both robust and non-robust path generation technique to evaluate our approach.
Chakraborty, Swati (2015). At-Speed Path Delay Test. Master's thesis, Texas A & M University. Available electronically from