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dc.contributor.advisorSanchez-Sinencio, Edgar
dc.creatorWang, Mengde
dc.date.accessioned2015-02-05T17:22:23Z
dc.date.available2016-08-01T05:30:18Z
dc.date.created2014-08
dc.date.issued2014-05-22
dc.date.submittedAugust 2014
dc.identifier.urihttps://hdl.handle.net/1969.1/153231
dc.description.abstractA Low Drop-Out (LDO) voltage regulator with both capacitor-less and high power supply rejection (PSR) bandwidth attributes is highly admired for an integrated power management system of mobile electronics. The capacitor-less feature is demanded for realizing more compact device. The high PSR bandwidth is essential for being used with high frequency switching regulators. These two attributes are of strong trade-off because usually a capacitor-less LDO requires Miller Compensation which greatly limits the PSR bandwidth. This thesis presents a LDO design with both capacitor-less and high PSR bandwidth attributes. The proposed LDO structure incorporates external compensation which is gifted for extended PSR bandwidth. A capacitance multiplier (CM) of high multiplication factor (≈ 100) is designed to externally compensate the LDO without an external off-chip capacitor. In the proposed LDO circuit, NMOS is used as the pass transistor for system stabilization. Triple-well NMOS and Zero-Vt NMOS are used as pass transistors in the two main LDO designs. The design with the triple-well NMOS pass transistor aims at higher PSR bandwidth with lower power consumption. The design with Zero-Vt NMOS pass transistor eliminates the necessity of a charge pump for driving the gate of a NMOS pass transistor. Implemented in IBM 0.18μm technology, the LDO with triple-well NMOS achieves -40dB PSR to 19MHz with 265μA current consumption. The LDO with Zero-Vt NMOS achieves -40dB PSR to 10MHz with 350μA current consumption. In thisdesign, the feasibility of using Zero-Vt NMOS as a LDO pass transistor is proved. Moreover, compared to traditional capacitor-less LDOs with PSR bandwidth around 10kHz and above 0dB PSR beyond 10MHz, the PSR bandwidth of the proposed LDO structure is greatly extended with significant PSR over 10MHz. This also proves the feasibility of applying external compensation strategy to a capacitor-less LDO and its great beneficial effect on the PSR of the LDO.en
dc.format.mimetypeapplication/pdf
dc.language.isoen
dc.subjectlow drop-out regulatoren
dc.subjectLDOen
dc.subjectexternally-compensationen
dc.subjectcapacitor-lessen
dc.subjectcapacitance multiplieren
dc.subjectpower supply rejectionen
dc.subjectPSRen
dc.titleA Capacitor-Less Wide-Band Power Supply Rejection Low Drop-Out Voltage Regulator with Capacitance Multiplieren
dc.typeThesisen
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorTexas A & M Universityen
thesis.degree.nameMaster of Scienceen
thesis.degree.levelMastersen
dc.contributor.committeeMemberEntesari, Kamran
dc.contributor.committeeMemberLi, Peng
dc.contributor.committeeMemberParlos, Alexander
dc.type.materialtexten
dc.date.updated2015-02-05T17:22:23Z
local.embargo.terms2016-08-01
local.etdauthor.orcid0000-0003-4932-6143


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