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dc.contributor.advisorHu, J.
dc.contributor.advisorMahapatra, R. N.
dc.creatorRajaram, Anand K.
dc.date.accessioned2004-11-15T19:45:10Z
dc.date.available2004-11-15T19:45:10Z
dc.date.created2004-08
dc.date.issued2004-11-15
dc.identifier.urihttp://hdl.handle.net/1969.1/1052
dc.description.abstractAs VLSI technology moves into the Ultra-Deep Sub-Micron (UDSM) era, manufacturing variations, power supply noise and temperature variations greatly affect the performance and yield of VLSI circuits. Clock Distribution Network (CDN), which is one of the biggest and most important nets in any synchronous VLSI chip, is especially sensitive to these variations. To address this problem variability-aware analysis and optimization techniques for VLSI circuits are needed. In the first part of this thesis an analytical bound for the unwanted skew due to interconnect variation is established. Experimental results show that this bound is safer, tighter and computationally faster than existing approaches. This bound could be used in variation-aware clock tree synthesis.The second part of the thesis deals with optimizing a given clock tree to minimize the unwanted skew variations. Non-tree CDNs have been recognized as a promising approach to overcome the variation problem. We propose a novel non-tree CDN obtained by adding cross links in an existing clock tree. We analyze the effect of the link insertion on clock skew variability and propose link insertion schemes. The non-tree CDNs so obtained are shown to be highly tolerant to skew variability with very little increase in total wire-length. This can be used in applications such as ASIC design where a significant increase in the total wire-length is unacceptable.en
dc.format.extent252841 bytesen
dc.format.extent82949 bytesen
dc.format.mediumelectronicen
dc.format.mimetypeapplication/pdf
dc.format.mimetypetext/plain
dc.language.isoen_US
dc.publisherTexas A&M University
dc.subjectVLSI Clock Distributionen
dc.subjectSkewen
dc.subjectVariationen
dc.titleAnalysis and optimization of VLSI Clock Distribution Networks for skew variability reductionen
dc.typeBooken
dc.typeThesisen
thesis.degree.departmentElectrical Engineeringen
thesis.degree.disciplineVocational Educationen
thesis.degree.grantorTexas A&M Universityen
thesis.degree.nameMaster of Scienceen
thesis.degree.levelMastersen
dc.contributor.committeeMemberWalker, D. M. H.
dc.contributor.committeeMemberSilva-Martinez, J.
dc.contributor.committeeMemberShi, W.
dc.type.genreElectronic Thesisen
dc.type.materialtexten
dc.format.digitalOriginborn digitalen


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