Now showing items 1-4 of 4

    • Chang, Chi-Yu (2012-10-19)
      In this thesis, we proposed an intermediate sub-process between placement and routing stage in physical design. The algorithm is for generating layer guidance for post-placement optimization technique especially buffer ...
    • Li, Zhuo (Texas A&M University, 2006-04-12)
      As the continuous trend of Very Large Scale Integration (VLSI) circuits technology scaling and frequency increases, delay optimization techniques for interconnect are increasingly important for achieving timing closure of ...
    • Wu, Di (Texas A&M University, 2006-08-16)
      As fabrication technology keeps advancing, many deep submicron (DSM) effects have become increasingly evident and can no longer be ignored in Very Large Scale Integration (VLSI) design. In this dissertation, we study several ...
    • Jiang, Zhanyuan (2009-05-15)
      As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out as an effective technique for timing optimization. A dramatic ...