Browsing by Subject "KLPG"

Now showing items 1-3 of 3

    • Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra 
      Biswas, Prasenjit (2016-08-04)
      Scan-based delay test achieves high fault coverage due to its improved controllability and observability. This is particularly important for our K Longest Paths Per Gate (KLPG) test approach, which has additional necessary ...
    • Path Delay Test Through Memory Arrays 
      Pokharel, Punj (2013-07-29)
      Memory arrays cannot be as easily tested as other storage elements in a chip. Most of the flip-flops (FFs) in a chip can be replaced by scan cells in scan-based design. However, the bits in memory arrays cannot be replaced ...
    • Pseudo Functional Path Delay Test through Embedded Memories 
      Gao, Yukun (2015-04-29)
      On-chip memory arrays are widely used in systems-on-chip. Prior research has shown that timing critical paths often go through these memories. Embedded memories are typically tested using memory built-in self-test and macro ...