Short-Time Scale Dynamic Failure Modes in a Through-Silicon-Via (TSV) Flip-Chip Configuration
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Date
2010-10-12
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Abstract
The demand for high performance microelectronic products drives the
development of 3-D chip-stacking structure. By the introduction of through-silicon-via
(TSV) into 3-D flip-chip packages, microelectronic performance is improved by
increasing circuit capacity and diminishing signal delay. However, TSV-embedded
structure also raises concerns over many reliability issues that come with the steep
thermal and mechanical transient responses, increasing numbers of bi-material interfaces
and reduced component sizes. In this research, defect initiation induced by thermalmechanical
phenomena is studied to establish the early failure modes within 3-D flip-chip
packages. It is found that low amplitude but extremely high frequency thermal
stress waves would occur and attenuate rapidly in the first hundreds of nanoseconds
upon power-on. Although the amplitude of these waves is far below material yielding
points, their intrinsic characteristics of high frequency and high power density are
capable of compromising the integrity of all flip-chip components. By conducting
spectral analysis of the stress waves and applying the methodology of accumulated
damage evaluation, it is demonstrated that micron crack initiation and interconnect debond are highly probable in the immediate proximity of the heat source. Such a
negative impact exerted by the stress wave in the early, while brief, transient period is
recognized as the short time scale dynamic effect. Researched results strongly indicate
that short-time scale effects would inflict very serious reliability issues in 3-D flip-chip
packages. The fact that 3-D flip-chip packages accommodate a large amount of
reduced-size interconnects makes it vulnerable to the attack of short time scale
propagating stress waves. In addition, the stacking structure also renders shearing effect
extremely detrimental to 3-D flip-chip integrity. Finally, several guidelines effective in
discouraging short-time scale effects and thus improving TSV flip-chip package
reliability are proposed
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Keywords
Flip-chip packages, Reliability, Short-time scale