Gallium Nitride Superjunctions for Power Electronic Applications
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Date
2019-07-16
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Abstract
Gallium Nitride (GaN) is a wide-band gap semiconductor that has found market acceptance in applications such as lighting, power electronics and radio-frequency electronics. The high breakdown electric field and electron saturation velocity of GaN are favorable relative to Silicon, but manufacturing costs and material defects have limited the market penetration of GaN. Commercial GaN devices are based on a two-dimensional electron gas (2DEG) that arises from spontaneous and piezoelectric polarization at the hetero-interface between GaN and Aluminum Gallium Nitride (AlGaN). These 2DEG-based devices, termed High Electron Mobility Transistors (HEMTs), have under-performed to date when comparing semiconductors with the Baliga Figure of Merit (BFOM) for power electronics. However, Silicon and Silicon Carbide (SiC) devices have exceeded their respective material limits due to lower defect density materials and device engineering. Currently, no native substrate for GaN is economically viable or commercially available so Group III-Nitrides are deposited on Si, Sapphire or SiC. This hetero-epitaxy leads to high defect densities in the epitaxial films which hinder device performance and reliability. Therefore, the reduction of defect densities and manufacturing costs is critical to meeting goals set-forth by government agencies to improve power conversion efficiencies while being cost competitive. The work presented herein provides a potential solution to manufacturing low defect density GaN devices that have both a low on-state resistance, RvON and high blocking voltage capability, VvBR, on Silicon substrates. This is accomplished by utilizing selective area epitaxy (SAE), which reduces the defect densities of the epitaxial films, and adopting the superjunction (SJ) device architecture from Silicon that reduces the engineering trade-off between RvON and VvBR. A SJ device requires n-type and p-type GaN materials (n-GaN and p-GaN, respectively), of which p-GaN has proven to be a material that is difficult to achieve in low resistivities. However, the doping ranges required to achieve high voltage operation have been frequently demonstrated. The SAE process requires extra lithography and deposition steps relative to a commercial GaN-on-Si HEMT technology, therefore the high growth rates of the SAE are leveraged to reduce deposition time and thinner buffers layers could enable larger wafer diameters. Parametric device simulations are presented to determine which design parameters are most sensitive in the superjunction process. The SJ layer charge and metal contact resistance to the pGaN were found to be the two most critical design parameters. Next, an epitaxial GaN process was developed on sapphire substrates using Metal Organic Chemical Vapor Deposition (MOCVD). The GaN-on-Sapphire films were characterized using Hall measurements and diodes to understand the background doping concentration of the unintentionally doped GaN (UID-GaN). These GaN films and devices serve as a baseline for comparing GaN films grown on Silicon substrates. Integration of GaN with Silicon control electronics is an attractive technology to reduce interconnect losses and minimize footprint. However, commercial GaN devices are grown on Silicon (111) substrates while CMOS devices are fabricated using Silicon (100). A GaN-on-Silicon (100) process was developed using Atomic Layer Deposition (ALD) Aluminum Oxide (Al2O3) as a nucleation layer, with the goal of understanding how GaN could be grown on Silicon (100) substrates to avoid costly bonding and substrate removal processes. X-ray Diffraction (XRD) and electrical characterization was utilized to compare the GaN quality between Silicon substrates and the GaN-on-Sapphire. A SAE process for GaN on Sapphire substrates was developed using a Plasma Enhanced CVD (PECVD) Silicon Nitride (Si3N4) dielectric as a mask. Scanning Electron Microscopy (SEM) was utilized to monitor lateral epitaxy and provide information on how to control the film morphology. Significant defect density reduction of the SAE GaN films was accomplished by using Aspect Ratio Trapping (ART), which is a form of SAE where the aspect ratio of the dielectric window is greater than 1. Electron beam lithography (EBL) and Reactive Ion etching (RIE) processes were developed to obtain an aspect ratio of 1.2. Transmission Electron Microscopy (TEM) was then performed on the ART GaN-on-Silicon (111) which verified defect trapping inside the windowed region. Lastly, p-GaN ohmic contacts were developed using Nickel and Gold as a baseline process. Improvements to the baseline ohmic contact process was made by using Magnesium as an interlayer between the p-GaN and the Nickel.
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Keywords
Gallium Nitride, Superjunction, Aspect Ratio Trapping, Selective Area Epitaxy, Ohmic Contacts, p-GaN