A High Frequency Multilevel Boost Power Factor Correction Approach with GaN Semiconductors
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Date
2020-04-16
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Abstract
This thesis presents a generalized multilevel power factor correction approach that utilizes low voltage GaN semiconductors, reduces inductor voltage, increases inductor current ripple frequency, and reduces capacitor voltage ratings to achieve a high power density and high efficiency design. The multilevel topology is fully modular and can be scaled to higher voltage levels while utilizing low voltage switching devices and capacitors, which can improve power density and efficiency. The topology also reduces the voltage stress across the input inductor to a fraction of the output voltage using fractional voltage levels and multiplies the effective inductor current ripple frequency compared to the traditional boost power factor correction circuit. These improvements allow a drastic reduction in the size of the input inductor. A review of GaN devices and recent advances in power factor correction topology design is conducted. The operating zones of the topology are described in detail as well as the switching states of the topology. A feedback controller design guide is presented for continuous conduction mode boost power factor correction. The switching control is designed for a topology with any number of levels and the multiplication of the inductor current ripple frequency is explained. Simulation results are presented to confirm the controller design and response under various loading conditions and source variations. A detailed design example describes the derivation of design equations for passive components and a guide for selecting appropriate high frequency passive components and designing capacitance and inductance values. Finally, hardware results are presented and future work concerning the topology is discussed.
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Multilevel, Power Factor Correction, PFC, Totem-Pole, GaN