Branch-directed Data Prefetching
| dc.contributor.committeeMember | Gratz, Paul V | |
| dc.creator | Shepherd, Scott James | |
| dc.date.accessioned | 2023-11-01T13:41:30Z | |
| dc.date.available | 2023-11-01T13:41:30Z | |
| dc.date.created | 2023-05 | |
| dc.date.submitted | May 2023 | |
| dc.date.updated | 2023-11-01T13:41:30Z | |
| dc.description.abstract | Memory prefetching in computer processors is the practice of predicting memory addresses that will need to be accessed and issuing requests to pull data from those addresses ahead of time. These circuits are crucial to combatting the "memory wall", a bottleneck in processor speed caused by the relatively slower progression of memory access speeds compared to progress in instruction execution speed. This project builds upon the Signature Path Prefetcher (SPP), a prefetcher for the L2C cache developed in Professor Gratz’s CAMSIN research group. The SPP decides prefetch addresses based on a delta access history signature. This project explores the possibility of enhancing the SPP by incorporating branch history data (branch decisions & target addresses) into the existing prefetcher structure. The Branch-Directed SPP aims to improve overall performance as measured by IPC speedup. Results show that the design performs similarly to baseline SPP across these metrics, outperforming slightly on some trace sets and underperforming slightly on others. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | https://hdl.handle.net/1969.1/200250 | |
| dc.subject | computer architecture | |
| dc.subject | memory | |
| dc.subject | prefetching | |
| dc.title | Branch-directed Data Prefetching | |
| dc.type | Thesis | |
| dc.type.material | text | |
| thesis.degree.department | Electrical and Computer Engineering | |
| thesis.degree.discipline | Electrical Engineering | |
| thesis.degree.grantor | Undergraduate Research Scholars Program | |
| thesis.degree.level | Undergraduate | |
| thesis.degree.name | B.S. |