Techniques for Analog Design Automation and Task Mapping for Finite Element Computing
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Date
2023-10-20
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Abstract
Analog Integrated Circuit (IC) design is usually a manual design process which requires human experts engagement and thus is labor-intensive. In addition, the design process often requires a lot of trial-and-error, which make it even more time-consuming. Although analog design automation has been widely researched for decades, the quality of automated generated design still falls far behind manual design.
Analog circuit performance highly depends on layout parasitic. Placement is an important step in analog layout design, as the placement pattern determines the distance between pins and sig-nificantly influences layout parasitic. However, there is few previous work that considers circuit performance in the placement stage. Most works optimize the shape of placement pattern including geometrical constraints, area and wire length. As machine learning technique has shown its advantages in estimation and inference, we propose to integrate machine learning techniques into analog circuit placement. This is known as performance driven placement, where machine learning models estimate the layout performance in the placement stage and guide the placer. In addition, we integrate analytical techniques in the placement stage, which significantly reduce placement area and wire length compared with previous works.
An issue related to circuit performance estimation is the estimation accuracy and runtime. Previous works are mostly building performance models for the entire circuit, which is hard to apply the model trained on one circuit to another circuit. Thus, the model construction cost is huge as model reusability and transferability is very limited. We propose a macro-modeling method, where each sub-circuit corresponds to a macro-model. These macro-models are reused in circuits of different topologies and even in different types of circuit. This strategy greatly reduces model construction cost and improves model accuracy.
Integrated circuits have wide applications, one of which is wafer scale supercomputer and can be applied in finite element computing. Finite element computing is a numerical technique to solve partial differential equation computing tasks. As finite element computing typically requires a lot of computing resources, wafer scale supercomputer becomes a good fit for finite element computing. A wafer scale supercomputer is composed of numerous CPU cores and is able to meet the computing resource requirement of finite element computing. For finite element computing on wafer scale supercomputer, several aspects are considered, where the most important ones are computing accuracy and computing speed. A key strategy is the computing resource allocation for each computing task, a.k.a. task mapping, which maps each computing task onto one CPU core and optimize computing accuracy and speed. Thus, a proper task mapping strategy is proposed in this thesis. The results show that the proposed method has higher accuracy and speed than other methods in most test cases.
This thesis focuses on developing techniques for analog IC design automation as well as task mapping for finite element computing.
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Integrated circuits, analog circuits, design automation, layout design, circuit placement, circuit performance modeling, machine learning, model reusability, finite element computing,