Cache Design and Analysis for Mitigating Hardware Security in Multicore Systems
Abstract
Security in computing systems has been considered one of the greatest challenges due to the ever changing threat landscape, the complexity of systems, the presence of vulnerabilities, and a multitude of other factors. Security issues can cause billion-dollar damage and can expose private information to the public. Hardware security, in particular, has become a new territory for exploitation, including the recent discovery of transient execution attacks such as Spectre and Meltdown. They reveal the perils of transient execution in modern processors with out-of-order (O3) and speculative execution. Consequently, numerous researchers are dedicated to improving the security of computing systems.
Furthermore, Spectre and Meltdown have reshaped memory safety. Historically, memory safety issues were attributed to software bugs and human errors, leading software security experts to develop defenses such as bound checking and sandboxing. However, it is crucial to recognize that transient instructions, arising from mispredicted branches, can bypass these software defenses, accessing privileged data and transmitting it through cache side channels.
In addition to hardware security, a program’s calling context serves crucial functions in various use cases like profiling, debugging, optimization, and security monitors. They rely on uniquely encoded calling contexts for easy identification and consistency across runs. Existing encoding methods often lack this uniqueness and consistency, requiring users to add additional steps for their needs.
To mitigate the transient execution attacks, we develop ReViCe, a secure cache design to get rid of the side effect so that cache side channel is no longer available. We introduce a victim cache to restore the cache states from misspeculation and a jitter to hide the existence of cache lines installed by speculative request. For memory safety, we present a uniform defense against both software and hardware memory safety violation by profiling and checking program invariants. We observe that most of the memory locations of a program are accessed by only a handful of instructions during normal executions. These "good" instructions can be formulated for the corresponding memory locations at the current calling context as invariants of the program. Based on the observation, we present WHISTLE which extends a CPU and cache design to profile and check invariants at runtime with reasonable overhead. Last, we identify an inefficiency of existing calling context encoding schemes used by WHISTLE and present a new calling context encoding (DCCE), a faster encoding scheme for clients to improve their runtime performance.
Description
Keywords
Hardware Security, Cache Design