Realistic fault modeling and quality test generation of combined delay faults
Date
2001
Authors
Journal Title
Journal ISSN
Volume Title
Publisher
Texas A&M University
Abstract
With increasing operating speed and shrinking technology, timing defects in integrated circuits are becoming increasingly important. The well established stuck-at-fault model is not sufficient because it is a static fault model and does not account for the dynamic behavior of the circuit. Due to the signal integrity problem, the testing of VLSI-chips is becoming more complex. A static test vector generated to test a defect in an integrated chip can be found ineffective under the effect of capacitively coupled lines. To cope up with these realistic testing problems, it is necessary to model the circuit defects by considering the capacitively coupling between lines. This needs a better fault model which can incorporate the local defects (such as bridging defects) as well as global defects (such as cross-talk). Also it is necessary to generate test vectors which maximize the delay effect due to these combined faults. The test vectors should be generated so as to detect the maximum number of defects in real chips. In this research, we model the combined effect of local and global faults, and the model is called a combined delay fault model. We use the transition delay fault model to model the local defects on each line. Various quality constraints are imposed during test generation so that better quality test vectors are achieved. We impose strong driving constraints on gates to maximize the transition delay and propagate the transition effect along the longest, robust paths to increase the detection of small timing defects. We compare the test generation results for ISCAS85 benchmark circuits and see how efficient our quality test vectors are in detecting these combined delay faults. Finally, we study the DOREME vectors in reference to their efficiency in detecting transition faults and compare our quality test vectors with DOREME test vectors.
Description
Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to [email protected], referencing the URI of the item.
Includes bibliographical references (leaves 55-57).
Issued also on microfiche from Lange Micrographics.
Includes bibliographical references (leaves 55-57).
Issued also on microfiche from Lange Micrographics.
Keywords
computer engineering., Major computer engineering.