A PLL Design Based on a Standing Wave Resonant Oscillator

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dc.contributor.advisorKhatri, Sunil P.
dc.contributor.committeeMemberLi, Peng
dc.contributor.committeeMemberKim, Eun Jung
dc.creatorKarkala, Vinay
dc.date.accessioned2011-10-21T22:03:34Z
dc.date.accessioned2011-10-22T07:13:22Z
dc.date.available2011-10-21T22:03:34Z
dc.date.available2011-10-22T07:13:22Z
dc.date.created2010-08
dc.date.issued2011-10-21
dc.date.submittedAugust 2010
dc.description.abstractIn this thesis, we present a new continuously variable high frequency standing wave oscillator and demonstrate its use in generating the phase locked clock signal of a digital IC. The ring based standing wave resonant oscillator is implemented with a plurality of wires connected in a mobius configuration, with a cross coupled inverter pair connected across the wires. The oscillation frequency can be modulated by coarse and fine tuning. Coarse modification is achieved by altering the number of wires in the ring that participate in the oscillation, by driving a digital word to a set of passgates which are connected to each wire in the ring. Fine tuning of the oscillation frequency is achieved by varying the body bias voltage of both the PMOS transistors in the cross coupled inverter pair which sustains the oscillations in the resonant ring. We validated our PLL design in a 90nm process technology. 3D parasitic RLCs for our oscillator ring were extracted with skin effect accounted for. Our PLL provides a frequency locking range from 6 GHz to 9 GHz, with a center frequency of 7.5 GHz. The oscillator alone consumes about 25 mW of power, and the complete PLL consumes a power of 28.5 mW. The observed jitter of the PLL is 2.56 percent. These numbers are significant improvements over the prior art in standing wave based PLLs.en
dc.format.mimetypeapplication/pdf
dc.identifier.urihttps://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8546
dc.language.isoen_US
dc.subjectVoltage Controlled Oscillatoren
dc.subjectVCOen
dc.subjectPhase Locked Loopen
dc.subjectPLLen
dc.subjectStanding Wave Resonant Oscillatoren
dc.subjectTraveling Wave Resonant Oscillatoren
dc.subjectFine Tuningen
dc.subjectCoarse Tuningen
dc.subjectTransmission lineen
dc.subjectParasitic Extractionen
dc.subjectLocking Rangeen
dc.subjectClock distributionen
dc.titleA PLL Design Based on a Standing Wave Resonant Oscillatoren
dc.typeThesisen
dc.type.genrethesisen
dc.type.materialtexten
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineComputer Engineeringen
thesis.degree.grantorTexas A&M Universityen
thesis.degree.levelMastersen
thesis.degree.nameMaster of Scienceen

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