Multi-Valued Register Simulations
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Date
2021-04-20
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Abstract
Shared read-write registers help processes in a shared-memory system to communicate by performing read and write operations on them. In this thesis, we study the wait-free simulations of
shared read-write registers using weaker shared registers, for two consistency conditions regularity and atomicity. We propose an algorithm which is a hybrid of the existing tree algorithm and
the clique algorithm such that it gives a trade-off between the two algorithms in the number of
read/write steps used and the number of base registers. We also explore if existing algorithms,
particularly the tree algorithm, can be extended to simulate multiple writer registers, since register
simulations in most prior works have been for single-writer registers.
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Keywords
Shared registers, Atomicity, Regularity, Wait-Free