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dc.contributor.advisorShi, Weiping
dc.creatorDoddannagari, Uday
dc.date.accessioned2010-01-15T00:08:04Z
dc.date.accessioned2010-01-16T00:33:21Z
dc.date.available2010-01-15T00:08:04Z
dc.date.available2010-01-16T00:33:21Z
dc.date.created2007-12
dc.date.issued2009-05-15
dc.identifier.urihttp://hdl.handle.net/1969.1/ETD-TAMU-2443
dc.description.abstractStandard-Cell-library-based design ow is widely followed in the Application Specific Integrated Circuit(ASIC) industry. Most of the realistic cell libraries are geometrically spaced introducing significant sparseness in the library. This is because uniformly spaced gate sizes would result in a large number of gate sizes and maintaining the huge volume of data for this number of gate sizes is difficult. This thesis aims to propose a practical approach to implement integer gate sizes. A parameterized cell (p-cell) approach to the generation of layouts of standard gates is presented. The use of constant delay model for gate delay estimation is proposed which eliminates the need for maintaining huge volumes of delay tables in the standard cell library. This approach has tremendous potential since it greatly simplifies the standard-cell-based design methodology and can give significant power and area savings.Power and area savings of up to 28% are possible using this approach.en
dc.format.mediumelectronicen
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.subjectp-cellen
dc.subjectdelay modelen
dc.titleA p-cell approach to integer gate sizingen
dc.typeBooken
dc.typeThesisen
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineComputer Engineeringen
thesis.degree.grantorTexas A&M Universityen
thesis.degree.nameMaster of Scienceen
thesis.degree.levelMastersen
dc.contributor.committeeMemberHu, Jiang
dc.contributor.committeeMemberJung, Yong-Kyu
dc.type.genreElectronic Thesisen
dc.type.materialtexten
dc.format.digitalOriginborn digitalen


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