Abstract
With growing complexity of today's ICs, it is desirable to improve traditional testing methods to increase the throughput. If one can select a limited number of points to test the circuit from a given test pattern, the time required for testing can be greatly reduced. A test point selection method has been proposed by Gerard N. Stenbakken and T. Michael Souders. Their work aims to reduce the redundancy in a test pattern. In order to use their algorithm, the circuit model must be first described by a sensitivity matrix obtained from first order derivative of circuit equations. However, the construction of this sensitivity matrix remains to be a difficult task. The purpose of this thesis is to explore a way for automatically generating the sensitivity matrix. From this matrix, a reduced size matrix can be obtained to reduce the number of test points. The following techniques and algorithms are used to achieve a reduced size sensitivity matrix: 1: Discrete wavelet transform (DWT): It is used to find the statistical features of the tested circuit outputs. These features are used to construct the sensitivity matrix. 2: Self-organizing-map(SOM): The features found in (1) are usually in a random order. By using SOM, the features are categorized and grouped together. 3: QRF with pivoting: This algorithm decomposes the matrix obtained using features classified by SOM into an orthogonal matrix and an upper triangular matrix. (4) D-optimality criterion: This criterion is used to select most important vectors in the upper triangular matrix and thus reduce the size of the matrix. The required number of test points is proportional to the size of the matrix. A reduction in the matrix size will minimize the number of required test points. It is shown in this thesis that by using DWT, QRF algorithm and feature classification tool, it is possible to automatically construct and implement sensitivity matrices for various devices under testing. By using only the small number of test points selected from a much larger set, the testing time is found to be reduced by one order of magnitude. The estimation error is within 2%.
Huang, Hsing-Chiang (2000). Test point selection using wavelet transforms for mixed-signal circuit. Master's thesis, Texas A&M University. Available electronically from
https : / /hdl .handle .net /1969 .1 /ETD -TAMU -2000 -THESIS -H83.