A new approach to test programmable wiring networks for VLSI

Abstract

The programmable nature of today's digital circuits such as FPGAs (field programmable gate arrays), PLDs (programmable logic devices) and FPICs (field pro-grammable interconnect chips) has made possible the manufacturing of complex digital systems with a substantial reliance on sophisticated interconnect (wiring network) resources. Therefore, the interconnect (wiring network) resources play an important role both for programming flexibility and performance of digital programmable chips. The occurrence of faults due to either shorts or opens in the nets, and stuck-ON/OFF in the switches, is of a major concern. A wiring network can be of two types: nonprogrammable wiring network (NPWN) and programmable wiring network (PWN). This thesis concentrates on the testing issues of a PWN. This thesis first presents a new approach to test a PWN for fault detection only. The proposed approach employs a divide-and-conquer technique. It is proved that it is always possible to decompose a PWN of maximal degree Dp into Dp node-disjoint path sets if every net in the PWN (except the input nets and the output nets) has the feature that the indegree is equal to the outdegree. Initially, the given PWN is decomposed into Dp node-disjoint path sets by using the maximum flow algorithm with upper and lower capacity bounds. Each path set can be tested in paxallel in a testing phase. Then, for the adjacencies not covered by the path sets generated through the PWN decomposition, a residual adjacency graph processing step is used to generate additional path sets to test them. Finally, a simple coloring algorithm and the modified counting sequence are used to generate the test vectors for each path set. AU algorithms described in this thesis have been implemented and simulation results have demonstrated the effectiveness of the proposed approach.