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dc.creatorHussain, Wajid
dc.date.accessioned2012-06-07T22:49:04Z
dc.date.available2012-06-07T22:49:04Z
dc.date.created1997
dc.date.issued1997
dc.identifier.urihttps://hdl.handle.net/1969.1/ETD-TAMU-1997-THESIS-H87
dc.descriptionDue to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to digital@library.tamu.edu, referencing the URI of the item.en
dc.descriptionIncludes bibliographical references: p. 101-106.en
dc.descriptionIssued also on microfiche from Lange Micrographics.en
dc.description.abstractRapid failure analysis and continuous monitoring of the fabrication line are required in order to maximize the slope of the semiconductor manufacturing yield ramp. Metrology costs are the fastest rising expense occurring in the fabrication line. In addition, many of the defects can only be detected using electrical methods. Hence the use of simulation-based models for defect diagnosis is on the increase. We have used an already available methodology of defect-fault dictionary building and have observed the effects of certain noise sources such as line width variation, sample size and bridge resistance on yield learning, and determined how to account for them. In this research we will show that since line width variation is not random on a few wafer samples, its effect on defect Pareto predictions is profound and must be collected. We will show that a linear model is sufficient to correct for the sensitivity of defect density to line width variation and shall also confirm this experimentally. We have examined the effect of various defect sample sizes on the resolution of the defect-fault dictionary and hence on the diagnosibility. We will show that the dictionary construction costs can be reduced by using relatively small sample sizes without a significant reduction in Pareto accuracy. We shall also show that a distribution of bridge resistance does not effect the Pareto accuracy. Our observations and correction model allow us to make accurate defect Pareto predictions in the presence of these noise sources.en
dc.format.mediumelectronicen
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherTexas A&M University
dc.rightsThis thesis was part of a retrospective digitization project authorized by the Texas A&M University Libraries in 2008. Copyright remains vested with the author(s). It is the user's responsibility to secure permission from the copyright holder(s) for re-use of the work beyond the provision of Fair Use.en
dc.subjectelectrical engineering.en
dc.subjectMajor electrical engineering.en
dc.titleYield learning with line width, sample size and bridge resistance variationen
dc.typeThesisen
thesis.degree.disciplineelectrical engineeringen
thesis.degree.nameM.S.en
thesis.degree.levelMastersen
dc.type.genrethesisen
dc.type.materialtexten
dc.format.digitalOriginreformatted digitalen


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