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dc.creatorPaul, Debjyoti
dc.date.accessioned2012-06-07T22:46:16Z
dc.date.available2012-06-07T22:46:16Z
dc.date.created1996
dc.date.issued1996
dc.identifier.urihttp://hdl.handle.net/1969.1/ETD-TAMU-1996-THESIS-P39
dc.descriptionDue to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to digital@library.tamu.edu, referencing the URI of the item.en
dc.descriptionIncludes bibliographical references: p. 73-78.en
dc.descriptionIssued also on microfiche from Lange Micrographics.en
dc.description.abstractWe describe a new approach for formal verification of combinational logic circuits using Recursive learning, ATPG and Transformations. A logic verification tool, VeriLAT, was implemented based on this approach. Experimental results on the ISCAS85 benchmark circuits have been included. The approach is shown to be fast and robust for a wide variety of circuits. It has been shown to be especially suited for verifying dissimilar circuits which cause a lot of problems to other approaches.en
dc.format.mediumelectronicen
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherTexas A&M University
dc.rightsThis thesis was part of a retrospective digitization project authorized by the Texas A&M University Libraries in 2008. Copyright remains vested with the author(s). It is the user's responsibility to secure permission from the copyright holder(s) for re-use of the work beyond the provision of Fair Use.en
dc.subjectcomputer science.en
dc.subjectMajor computer science.en
dc.titleLogic verification using recursive learning, ATPG and transformationsen
dc.typeThesisen
thesis.degree.disciplinecomputer scienceen
thesis.degree.nameM.S.en
thesis.degree.levelMastersen
dc.type.genrethesisen
dc.type.materialtexten
dc.format.digitalOriginreformatted digitalen


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