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Design of a multithreaded instruction cache for a hyperscalar processor
|dc.description||Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to email@example.com, referencing the URI of the item.||en|
|dc.description||Includes bibliographical references.||en|
|dc.description.abstract||A Multithreaded instruction cache design for a Superscalar architecture supporting the concurrent execution of multiple independent instruction streams, termed as Hyperscalar is presented. The Hyperscalar architecture enhances the instruction issue rate by providing multiple functional units and improves resource utilization by supporting multiple instruction threads. The cache is lock up free, and is able to accept multiple requests which are stored in an input request queue. The cache can simultaneously resolve a miss generated by one instruction thread while satisfying a request for another instruction thread. The cache is set associative and is shared between the threads. A simulation model is developed to evaluate and compare the performance of the cache using trace driven simulations. Simulation results show a small cache can support two to four threads. A BICMOS circuit level implementation of the read access path in a typical set associative cache is used to estimate the average cache access time.||en|
|dc.publisher||Texas A&M University|
|dc.rights||This thesis was part of a retrospective digitization project authorized by the Texas A&M University Libraries in 2008. Copyright remains vested with the author(s). It is the user's responsibility to secure permission from the copyright holder(s) for re-use of the work beyond the provision of Fair Use.||en|
|dc.subject||Major electrical engineering.||en|
|dc.title||Design of a multithreaded instruction cache for a hyperscalar processor||en|
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