Semantic gap reduction for microprocessor systems

Abstract

The objective of this dissertation is to design an instruction set that will reduce the semantic gap (the difference between the concepts in HLPL's-- high level programming languages-- and the architecture of a computer system). This dissertation only concentrates on the design of an architecture for one of the class of HLPL's that was selected for implementation on a microprocessor based computing system. The principle of the M3 S D (multilingual multiarchitecture multiprocessor system design) that is outlined in this research requires that all the HLPL's to be supported by a system be grouped according to the program structures and the semantics of the HLPL's to be supported. Each system will have several instruction sets. Each class of HLPL's will have its own instruction set tailored towards that class of HLPL's. Each architecture will be evaluated, optimized, and implemented. Architectural issues will be based on HLPL's being supported and implementation issues will be based on cost, speed required, and technology. The use of bottom-up design principles and the neglect of HLPL's needs by architects in most architectures are the prime cause of the semantic gap. The M3 S D design principle outlined in this research is a viable solution to the problems of bottom-up design and the inconsistent support for HLPL's on architectures. The design principle outlined for designing instruction sets is also a viable alternative to the current design principles used in CISC's (complex instruction set computers) and RISC's (reduced instruction set computers). Rather than basing instruction set designs on ad hoc or object code-dependent statistics, instruction set designs are based on HLPL's semantics and influenced by the structures of programs written in the HLPL's being supported.