Design issues in a new implementation approach to digital fault simulators for protective relay studies

Abstract

After almost a century of continuous growth, modern power systems are facing contradicting demands of increasing the existing network utilization while improving the overall service reliability. This puts special emphasis on the performance of power system protection and control devices, making it necessary to revise old, and design new protection schemes based on the use of latest signal processing and communication technology. The development of new devices has been slowed by the lack of adequate design tools capable of faithfully reproducing the power system behavior in the controlled laboratory environment. The goal of this thesis is to demonstrate main aspects associated with hardware architecture, design and implementation of digital power system simulators optimized for protective relay studies. This is achieved by classifying the designs into 2 categories: open loop, and closed loop (real-time) simulators. After analyzing the design requirements, a new open loop simulator design architecture based on a distributed waveform reconstruction system is proposed. It is followed with the theoretical discussion of clock generation and distribution mechanisms, variable sampling frequency and system synchronization support. All results are demonstrated on the actual open loop simulator prototype. Closed loop simulators are approached by using the EMTP program properties to identify the general real-time simulation program model. Use of this model is demonstrated on the design of a coarse-grain interaction real-time simulator built using the IBM RS6000/580 workstation aided by four TMS320C40 DSP processors. The system is capable of sustaining real-time operation with 50-100$mu$s time step and RS6000 CPU utilization exceeding 90%.