Design of High-Speed High-Resolution SAR ADC Exploiting Inherent Residue Computation
Abstract
Successive Approximation Register (SAR) ADCs are popular in RF receiver front ends especially in cell-phone applications due its low power. SAR ADCs also enjoy performance improvement on moving to lower process nodes. IEEE802.11ac standard defines the highest bandwidth as 80 MHz. To have suitable margins for digital processing, the ADCs in the receiver require sampling speed of 320 MS/s with a signal to noise ratio of 8 - 10 bits to satisfy the noise budget. Increasing resolution is a challenge because one bit extension requires 2X increase in CDAC (Capacitive Digital to Analog Converter). With an increase in circuit area, it also increases the settling times. At higher speeds it becomes extremely critical to meet the timing specification of the SAR feedback loop. This research project aims to extend resolution at high speeds without increasing the CDAC size. Thus there is no additional timing constraint over the original SAR.
The SAR ADC is implemented in TSMC 40nm process. Schematic simulations show that it achieves a sampling speed of 320 MS/s with an SNDR of 58.4 dB (9.4 bits) at Nyquist. The power consumption reported is 10.23mW .Other than the digital logic for resolution extension it also involves a semi-synchronous digital logic which relaxes the timing requirements.
Citation
Sharma, Utkarsh (2021). Design of High-Speed High-Resolution SAR ADC Exploiting Inherent Residue Computation. Master's thesis, Texas A&M University. Available electronically from https : / /hdl .handle .net /1969 .1 /195356.