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dc.creatorGunnam, Kiran Kumar
dc.creatorChoi, Gwan S.
dc.date.accessioned2019-06-17T17:08:20Z
dc.date.available2019-06-17T17:08:20Z
dc.date.issued2014-02-18
dc.identifier.urihttp://hdl.handle.net/1969.1/177060
dc.description.abstractA method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.en
dc.languageeng
dc.publisherUnited States. Patent and Trademark Office
dc.rightsPublic Domain (No copyright - United States)en
dc.rights.urihttp://rightsstatements.org/vocab/NoC-US/1.0/
dc.titleLow density parity check decoder for regular LDPC codesen
dc.typeUtility patenten
dc.format.digitalOriginreformatted digitalen
dc.description.countryUS
dc.contributor.assigneeTexas A&M University System
dc.identifier.patentapplicationnumber13/693650
dc.subject.uspcprimary714/758
dc.subject.uspcother714/801
dc.date.filed2012-12-04
dc.publisher.digitalTexas A&M University. Libraries


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