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dc.creatorAhmed, Ramy
dc.creatorHoyos, Sebastian
dc.creatorSilva-martinez, Jose
dc.date.accessioned2019-06-17T17:06:18Z
dc.date.available2019-06-17T17:06:18Z
dc.date.issued2012-04-24
dc.identifier.urihttps://hdl.handle.net/1969.1/176987
dc.description.abstractA continuous-time delta-sigma analog-to-digital converter (ADC) is disclosed. The ADC includes a loop filter, a loop quantizer, and a clock-jitter tolerant digital-to-analog converter (DAC). The clock-jitter tolerant DAC includes a dual switched-current (SI) DAC, a switched-capacitor (SC) DAC, an adder, and a switched-capacitor-resistor (SCR) injection circuit. The dual SI DAC provides two identical analog signals from the feedback digital signal of a loop quantizer within the ADC. The SC DAC provides an error-free reference signal from the feedback digital signal. The adder subtracts one of the two analog signals from the error-free reference signal to obtain an inverted jitter-induced error signal. The SCR injection circuit then injects the inverted jitter-induced error signal, delayed by one clock-cycle, in the form of a half-delay return-to-zero exponentially decaying waveform into the loop filter.en
dc.languageeng
dc.publisherUnited States. Patent and Trademark Office
dc.rightsPublic Domain (No copyright - United States)en
dc.rights.urihttp://rightsstatements.org/vocab/NoC-US/1.0/
dc.titleJitter cancellation method for continuous-time sigma-delta modulatorsen
dc.typeUtility patenten
dc.format.digitalOriginreformatted digitalen
dc.description.countryUS
dc.contributor.assigneeUniversity, Texas A&M
dc.identifier.patentapplicationnumber12/885605
dc.subject.uspcprimary341/143
dc.date.filed2010-09-20
dc.publisher.digitalTexas A&M University. Libraries
dc.subject.cpcprimaryH03M 3/372


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