|dc.description.abstract||In the past few years, power efficiency has been increasingly important for integrated circuits.
As the Moore’s law effects slows down, the improvement of power consumption through scaling
of silicon process technology is hitting the limits. At the same time, IC chips are more often embedded
into mobile devices, which usually have no outer continuous power supply. The power
efficiency is even more critical due to the limited electricity stored in batteries of these mobile
devices. Besides, the high-performance ICs used in server farms or data centers also require improved
power efficiency to alleviate the heat dissipation of the chips, which causes additional cost
to lower the temperature of the facilities. The profit of crypto-currency mining is even directly
affected by the electrical energy consumption of the mining hardware including ASICs, GPUs and
FPGAs, which accounts for the largest part of the cost. Thus, more techniques for power efficiency
were exploited in recent years to achieve further power reduction in addition to that achieved by
silicon process advancements.
Among the techniques for improving power efficiency, approximate computing has been recognized
as an effective low power technique for applications with intrinsic error tolerance, such
as image processing and machine learning. Existing efforts on this are mostly focused on approximate
circuit design, approximate logic synthesis or processor architecture approximation techniques.
Chapter 2 of this research aims to make good use of approximate circuits at system and
block levels. In particular, approximation aware scheduling, functional unit allocation and binding
algorithms are developed for data intensive applications. Simple yet credible error models, essential
for precision control in the optimizations, are investigated. The algorithms are further extended
to include bitwidth optimization in fixed point computations. Experimental results, including those
from Verilog simulations, indicate that the proposed techniques facilitate desired energy savings
under latency and accuracy constraints.
With their flexibility in allowing reconfiguration for different applications, hardware such as
FPGAs have become increasingly preferred over ASICs as a platform for high-performance comii
puting like accelerators. However, this advantage is partially defeated by the time-intensive highlevel
synthesis (HLS) process and the poor controllability for the synthesized architecture. We
propose a fast mapping-based high level synthesis technique friendly to local incremental change.
It exploits the SSA (Static Single Assignment) form with array SSA extension and ϕ-function
based flow control. It first maps the SSA form based IR to a fully pipelined circuit, then alters
the circuit to a partially pipelined or nonpipelined circuit by resource sharing in an optional phase
of resource optimization. Pipeline interlocking to address the pipeline hazards is also provided,
which has better power-efficiency.
Adaptive Supply Voltage (ASV) is another power-efficient approach to achieving resilience
against process variation and circuit aging. Fine-grained ASV offers further power efficiency gains,
but entails relatively complex control circuit, which has not been well studied yet. Chapter 4 of this
research presents two control design techniques: one is rule-based control derived from network
flow optimization and the other is finite state machine control. For the FSM control, a graph-based
algorithm that automates the control vector generation is proposed. This research also presents
an iterative greedy heuristic for delay sensor deployment in ASV designs. The effectiveness of
these techniques is confirmed by experiments performed on ICCAD 2014 benchmark circuits. The
results show that our techniques achieve around 20% leakage power reduction compared to coarsegrained ASV, while maintain about the same timing yield.||en