dc.contributor.advisor | Palermo, Samuel | |
dc.creator | Roshan Zamir, Ashkan | |
dc.date.accessioned | 2019-01-17T21:21:51Z | |
dc.date.available | 2020-05-01T06:23:12Z | |
dc.date.created | 2018-05 | |
dc.date.issued | 2018-05-08 | |
dc.date.submitted | May 2018 | |
dc.identifier.uri | https://hdl.handle.net/1969.1/173598 | |
dc.description.abstract | While the majority of wireline standards use simple binary non-return-to-zero (NRZ) signaling, four-level pulse-amplitude modulation (PAM4) standards are emerging to increase bandwidth density. This dissertation proposes efficient implementations for high speed NRZ/PAM4 transceivers. The first prototype includes a dual-mode NRZ/PAM4 serial I/O transmitter which can support both modulations with minimum power and hardware overhead. A source-series-terminated (SST) transmitter achieves 1.2Vpp output swing and employs lookup table (LUT) control of a 31-segment output digital-to-analog converter (DAC) to implement 4/2-tap feed-forward equalization (FFE) in NRZ/PAM4 modes, respectively. Transmitter power is improved with low-overhead analog impedance control in the DAC cells and a quarter-rate serializer based on a tri-state inverter-based mux with dynamic pre-driver gates. The transmitter is designed to work with a receiver that implements an NRZ/PAM4 decision feedback equalizer (DFE) that employs 1 finite impulse response (FIR) and 2 infinite impulse response (IIR) taps for first post-cursor and long-tail ISI cancellation, respectively. Fabricated in GP 65-nm CMOS, the transmitter occupies 0.060mm² area and achieves 16Gb/s NRZ and 32Gb/s PAM4 operation at 10.4 and 4.9 mW/Gb/s while operating over channels with 27.6 and 13.5dB loss at Nyquist, respectively. The second prototype presents a 56Gb/s four-level pulse amplitude modulation (PAM4) quarter-rate wireline receiver which is implemented in a 65nm CMOS process. The frontend utilize a single stage continuous time linear equalizer (CTLE) to boost the main cursor and relax the pre-cursor cancelation requirement, requiring only a 2-tap pre-cursor feed-forward equalization (FFE) on the transmitter side. A 2-tap decision feedback equalizer (DFE) with one finite impulse response (FIR) tap and one infinite impulse response (IIR) tap is employed to cancel first post-cursor and longtail inter-symbol interference (ISI). The FIR tap direct feedback is implemented inside the CML slicers to relax the critical timing of DFE and maximize the achievable data-rate. In addition to the per-slice main 3 data samplers, an error sampler is utilized for background threshold control and an edge-based sampler performs both PLL-based CDR phase detection and generates information for background DFE tap adaptation. The receiver consumes 4.63mW/Gb/s and compensates for up to 20.8dB loss when operated with a 2- tap FFE transmitter. The experimental results and comparison with state-of-the-art shows superior power efficiency of the presented prototypes for similar data-rate and channel loss. The usage of proposed design techniques are not limited to these specific prototypes and can be applied for any wireline transceiver with different modulation, data-rate and CMOS technology. | en |
dc.format.mimetype | application/pdf | |
dc.language.iso | en | |
dc.subject | Decision feedback equalizer (DFE) | en |
dc.subject | dual-mode serial link | en |
dc.subject | feed-forward equalizer (FFE) | en |
dc.subject | impedance tuning | en |
dc.subject | infinite impulse response (IIR) | en |
dc.subject | Non-Return to Zero(NRZ) | en |
dc.subject | Pulse Amplitude Modulation 4 (PAM4), receiver, transmitter | en |
dc.title | High Speed Reconfigurable NRZ/PAM4 Transceiver Design Techniques | en |
dc.type | Thesis | en |
thesis.degree.department | Electrical and Computer Engineering | en |
thesis.degree.discipline | Electrical Engineering | en |
thesis.degree.grantor | Texas A & M University | en |
thesis.degree.name | Doctor of Philosophy | en |
thesis.degree.level | Doctoral | en |
dc.contributor.committeeMember | Hoyos, Sebastian | |
dc.contributor.committeeMember | Narayanan, Krishna | |
dc.contributor.committeeMember | Zoghi, Behbood B | |
dc.type.material | text | en |
dc.date.updated | 2019-01-17T21:21:52Z | |
local.embargo.terms | 2020-05-01 | |
local.etdauthor.orcid | 0000-0002-6518-4424 | |