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dc.contributor.advisorHu, Jiang
dc.contributor.advisorSánchez-Sinencio, Edgar
dc.creatorWang, Jiafan
dc.date.accessioned2018-02-05T21:22:48Z
dc.date.available2019-08-01T06:51:52Z
dc.date.created2017-08
dc.date.issued2017-08-03
dc.date.submittedAugust 2017
dc.identifier.urihttps://hdl.handle.net/1969.1/166093
dc.description.abstractThe past few decades witness the burgeoning development of integrated circuit in terms of process technology scaling. Along with the tremendous benefits coming from the scaling, challenges are also presented in various stages. During the design time, the complexity of developing a circuit with millions to billions of smaller size transistors is extended after the variations are taken into account. The difficulty of analyzing these nondeterministic properties makes the allocation scheme of redundant resource hardly work in a cost-efficient way. Besides fabrication variations, analog circuits are suffered from severe performance degradations owing to their physical attributes which are vulnerable to aging effects. As such, the post-silicon calibration approach gains increasing attentions to compensate the performance mismatch. For the user-end applications, additional system failures result from the pirated and counterfeited devices provided by the untrusted semiconductor supply chain. Again analog circuits show their weakness to this threat due to the shortage of piracy avoidance techniques. In this dissertation, we propose three adaptive integrated circuit designs to overcome these challenges respectively. The first one investigates the variability-aware gate implementation with the consideration of the overhead control of adaptivity assignment. This design improves the variation resilience typically for digital circuits while optimizing the power consumption and timing yield. The second design is implemented as a self-validation system for the calibration of diverse analog circuits. The system is completely integrated on chip to enhance the convenience without external assistance. In the last design, a classic analog component is further studied to establish the configurable locking mechanism for analog circuits. The use of Satisfiability Modulo Theories addresses the difficulty of searching the unique unlocking pattern of non-Boolean variables.en
dc.format.mimetypeapplication/pdf
dc.language.isoen
dc.subjectLagrangian optimizationen
dc.subjectgate implementation and selectionen
dc.subjectadaptive circuiten
dc.subjectself-tuningen
dc.subjectmeta-heuristicen
dc.subjectanalog control systemen
dc.subjectband pass filteren
dc.subjectmicroprocessoren
dc.subjecthardware securityen
dc.titleAdaptive Integrated Circuit Design for Variation Resilience and Securityen
dc.typeThesisen
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineComputer Engineeringen
thesis.degree.grantorTexas A & M Universityen
thesis.degree.nameDoctor of Philosophyen
thesis.degree.levelDoctoralen
dc.contributor.committeeMemberLi, Peng
dc.contributor.committeeMember(Hank) Walker, Duncan M.
dc.type.materialtexten
dc.date.updated2018-02-05T21:22:49Z
local.embargo.terms2019-08-01
local.etdauthor.orcid0000-0002-2955-1469


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