| dc.description.abstract | Organic compounds have been regarded as insulators for a long time. However, a semi-conductive organic material was discovered in the late 1940s. Since then, many organic semiconductors have been found and studied. However, the current carriers have quite lower mobility than those of inorganic counterparts so far. In spite of the low mobility, organic semiconductor devices have many interesting advantages such as low-cost fabrication, easy process, diverse substrate materials, and so on. Owing to the benefit of the low-cost fabrication, organic semiconductor can be applied to large-area electronic devices as well as ubiquitous devices. Although organic semiconductor has been widely utilized in electronics, its low performance has extremely restricted application in integrated circuits (ICs) that are essential for high-tech electronics. In order to be competitive in market, the performance improvement of organic thin film transistors (OTFTs) has become an indispensable prerequisite. Although the low performance of conventional OTFTs basically results from the inherent low carrier mobility, it is also attributed to low resolution fabrication processes and their inferior configuration with large parasitic capacitance.
With regard to solutions to improve the performance of OTFTs, three novel strategies are proposed in this work: submicron metal patterning, self-aligned structure, and metal semiconductor field-effect transistor (MESFET)-like structure. To realize the solutions, a new concept of lithography, dual-layer thermal nanoimprint, is devised and its potential for submicron organic semiconductor patterning is experimented. In addition to the submicron resolution, two innovative patterning techniques, single-layer patterning and double-layer patterning, are successfully developed through the dual-layer thermal nanoimprint. Both patterning techniques can be utilized in fabricating self-aligned OTFTs and organic metal semiconductor field-effect transistors (OMESFETs). In the case of OMESFETs that require multiple-level metallization, the application of the dual-layer thermal nanoimprint lithography is extended from two-dimension to three-dimension to achieve self-aligned metallization that completely eliminates alignment errors. The 3D dual-layer thermal nanoimprint enables a sub-100 nm gap between metal patterns on an organic active layer. Because of the capability of nanoscale metal patterning on organic semiconductors with high overlay accuracy, this self-aligned metallization technique can be effectively utilized to fabricate high-performance top-contact OMESFETs. | en |
