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dc.contributor.advisorGratz, Paul V
dc.contributor.advisorHu, Jiang
dc.creatorSharma, Prabal
dc.date.accessioned2013-12-16T20:11:39Z
dc.date.available2013-12-16T20:11:39Z
dc.date.created2013-08
dc.date.issued2013-08-01
dc.date.submittedAugust 2013
dc.identifier.urihttp://hdl.handle.net/1969.1/151289
dc.description.abstractModern superscalar pipelines have tremendous capacity to consume the instruction stream. This has been possible owing to improvements in process technology, technology scaling and microarchitectural design improvements that allow programs to speculate past control and data dependencies in the superscalar architecture. However, the speed of the memory subsystem lags behind due to physical constraints in bringing in huge amounts of data to the processor core. Cache hierarchies have subdued the impact of this speed gap; however, there is much that can be still done in improving microarchitecture. Data prefetching techniques bring in memory content significantly before the instruction stream actually witnesses demand misses. However, a majority of the techniques proposed so far depend upon an initial demand miss that initiates a stream of previously identified prefetches. In this thesis, we propose a novel prefetching algorithm, which leverages branch prediction to facilitate deep memory system speculation. The branch predictor directed lookahead mechanism builds a speculative control flow path for the instruction stream about to be fetched by the main superscalar pipeline. Prefetches are generated along this speculative path from a condensed representation of the memory instructions, leveraging register index based correlation. The technique integrates eloquently with the main pipeline's branch predictor to filter out prefetches along invalid speculative paths. Impact of the prefetching scheme is analyzed using out- of-order model of the Gem5 cycle accurate simulator. Evaluation shows that on a set of 13 memory intensive SPEC CPU2006 benchmarks, our prefetching technique improves performance by an average of 5.6% over the baseline out-of-order processor.en
dc.format.mimetypeapplication/pdf
dc.language.isoen
dc.subjectprefetcheren
dc.subjectbranch directeden
dc.subjectlookaheaden
dc.subjectdata cacheen
dc.subjectauxiliary pipelineen
dc.subjectprimary cacheen
dc.subjectmshren
dc.titleA Branch Predictor Directed Data Cache Prefetcher for Out-of-order and Multicore Processorsen
dc.typeThesisen
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineComputer Engineeringen
thesis.degree.grantorTexas A & M Universityen
thesis.degree.nameMaster of Scienceen
thesis.degree.levelMastersen
dc.contributor.committeeMemberJimenez, Daniel A
dc.type.materialtexten
dc.date.updated2013-12-16T20:11:39Z


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