Browsing by Subject "VLSI"
Now showing items 1-20 of 25
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(2016-04-28)With its low error-floor performance, polar codes attract significant attention as the potential standard error correction code (ECC) for future communication and data storage. However, the VLSI implementation complexity ...
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(2021-04-01)In this dissertation, we propose two algorithms for semiconductor modeling and classification to utilize machine learning techniques. The first algorithm we propose is an automatic approach that significantly reduces the ...
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(Texas A&M University, 2007-04-25)Along the history of Very Large Scale Integration (VLSI), we have successfully scaled down the size of transistors, scaled up the speed of integrated circuits (IC) and the number of transistors in a chip - these are just ...
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(2012-10-19)In this thesis, we proposed an intermediate sub-process between placement and routing stage in physical design. The algorithm is for generating layer guidance for post-placement optimization technique especially buffer ...
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(2009-05-15)Moore’s Law has driven a continuous demand for decreasing feature sizes used in Very Large Scale Integrated (VLSI) technology which has outpaced the solutions offered by lithography hardware. Currently, a light wavelength ...
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(Texas A&M University, 2007-09-17)With shrinking feature size and growing integration density in the Deep Sub- Micron (DSM) technologies, the global buses are fast becoming the "weakest-links" in VLSI design. They have large delays and are error-prone. ...
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(2009-05-15)As VLSI technology scales to 65nm and below, traditional communication between design and manufacturing becomes more and more inadequate. Gone are the days when designers simply pass the design GDSII file to the foundry and ...
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(2013-05-02)As VLSI fabrication technology scales, an increasing number of processing elements (cores) on a chip makes on-chip communication a new performance bottleneck. The Network-on-Chip (NoC) paradigm has emerged as an efficient ...
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(2009-05-15)Fault diagnosis plays an important role in improving the circuit design process and the manufacturing yield. With the increasing number of gates in modern circuits, determining the source of failure in a defective circuit ...
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(2021-05-04)To realize the full potential of autonomous navigation, computing at the edge of network infrastructure is critical in reducing response times. In navigation systems, high-performance computing resources are often necessary ...
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(Texas A&M University, 2005-11-01)A high throughput scalable decoder architecture, a tiling approach to reduce the complexity of the scalable architecture, and two low power decoding schemes have been proposed in this research. The proposed scalable design ...
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Highly Parallel Algorithms and Systems for fast Electromagnetic Transient Simulation in Power System (2021-01-27)The significant increase of variable energy resources in the power grid, coupled with the substantial growth of electrified vehicles, leads to a more stressed grid with much higher variabilities at the operational stage. ...
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(2010-01-16)Circuit designers perform optimization procedures targeting speed and power during the design of a circuit. Gate sizing can be applied to optimize for speed, while Dual-VT and Dynamic Voltage Scaling (DVS) can be applied ...
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(2012-02-14)Gate sizing and threshold voltage (Vt) assignment are very popular and useful techniques in current very large scale integration (VLSI) design flow for timing and power optimization. Lagrangian relaxation (LR) is a common ...
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(2015-08-11)VLSI technology scaling has caused interconnect delay to increasingly dominate the overall chip performance. Optimization techniques such as buffer insertion, wire sizing and layer assignment play critical roles in successful ...
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(Texas A&M University, 2006-08-16)As fabrication technology keeps advancing, many deep submicron (DSM) effects have become increasingly evident and can no longer be ignored in Very Large Scale Integration (VLSI) design. In this dissertation, we study several ...
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(2009-05-15)This thesis presents a low-power LDPC decoder design based on speculative scheduling of energy necessary to decode dynamically varying data frame in both block-fading channels and general AWGN channels. A model of a ...
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(2021-10-27)As the cost of scaling-down the manufacturing process of integrated circuits grows larger and its performance gains become smaller, designs must grow in complexity in order to achieve expected performance improvements. As ...
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(2009-05-15)Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has ...
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(2014-12-11)As IC technology continues to follow the Moore’s Law, IC designers have been constantly challenged with power delivery issues. While useful power must be reliably delivered to the on-die functional circuits to fulfill the ...