Browsing by Subject "Power Supply Noise"

Now showing items 1-3 of 3

Efficient On-Chip Power Supply Sampling to Improve Post-Silicon Debug

Murray, Luke (2014-10-15)

In recent years, post-silicon debugging has become a significantly difficult exercise due to the increase in the size of the electrical state of the IC being debugged, coupled with the limited fraction of this state that ...
High Quality Test Generation Targeting Power Supply Noise

Zhang, Tengteng (2015-12-08)

Delay test is an essential structural manufacturing test used to determine the maximal frequency at which a chip can run without incurring any functional failures. The central unsolved challenge is achieving high delay ...
Low Cost Power and Supply Noise Estimation and Control in Scan Testing of VLSI Circuits

Jiang, Zhongwei (2012-02-14)

Test power is an important issue in deep submicron semiconductor testing. Too much power supply noise and too much power dissipation can result in excessive temperature rise, both leading to overkill during delay test. ...