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dc.contributor.advisorKim, Eun Jungen_US
dc.creatorAn, Baik Songen_US
dc.date.accessioned2012-10-19T15:30:37Zen_US
dc.date.accessioned2012-10-22T18:00:31Z
dc.date.available2014-11-03T19:49:13Z
dc.date.created2012-08en_US
dc.date.issued2012-10-19en_US
dc.date.submittedAugust 2012en_US
dc.identifier.urihttp://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11665en_US
dc.description.abstractHigh performance systems have been widely adopted in many fields and the demand for better performance is constantly increasing. And the need of powerful yet flexible systems is also increasing to meet varying application requirements from diverse domains. Also, power efficiency in high performance computing has been one of the major issues to be resolved. The power density of core components becomes significantly higher, and the fraction of power supply in total management cost is dominant. Providing dependability is also a main concern in large-scale systems since more hardware resources can be abused by attackers. Therefore, designing high-performance, power-efficient and secure systems is crucial to provide adequate performance as well as reliability to users. Adhering to using traditional design methodologies for large-scale computing systems has a limit to meet the demand under restricted resource budgets. Interconnecting a large number of uniprocessor chips to build parallel processing systems is not an efficient solution in terms of performance and power. Chip multiprocessor (CMP) integrates multiple processing cores and caches on a chip and is thought of as a good alternative to previous design trends. In this dissertation, we deal with various design issues of high performance multiprocessor systems based on CMP to achieve both performance and power efficiency while maintaining security. First, we propose a fast and secure off-chip interconnects through minimizing network overheads and providing an efficient security mechanism. Second, we propose architectural support for fast and efficient memory protection in CMP systems, making the best use of the characteristics in CMP environments and multi-threaded workloads. Third, we propose a new router design for network-on-chip (NoC) based on a new memory technique. We introduce hybrid input buffers that use both SRAM and STT-MRAM for better performance as well as power efficiency. Simulation results show that the proposed schemes improve the performance of off-chip networks through reducing the message size by 54% on average. Also, the schemes diminish the overheads of bounds checking operations, thus enhancing the overall performance by 11% on average. Adopting hybrid buffers in NoC routers contributes to increasing the network throughput up to 21%.en_US
dc.format.mimetypeapplication/pdfen_US
dc.language.isoen_USen_US
dc.subjectcomputer architectureen_US
dc.subjectchip multiprocessoren_US
dc.subjectnetwork-on-chipen_US
dc.titleArchitectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systemsen_US
dc.typeThesisen
thesis.degree.departmentComputer Science and Engineeringen_US
thesis.degree.disciplineComputer Scienceen_US
thesis.degree.grantorTexas A&M Universityen_US
thesis.degree.nameDoctor of Philosophyen_US
thesis.degree.levelDoctoralen_US
dc.contributor.committeeMemberCaverlee, Jamesen_US
dc.contributor.committeeMemberGu, Guofeien_US
dc.contributor.committeeMemberGautam, Natarajanen_US
dc.type.genrethesisen_US
dc.type.materialtexten_US
local.embargo.terms2014-10-22en_US


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