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dc.contributor.advisorHu, Jiangen_US
dc.contributor.advisorShi, Weipingen_US
dc.creatorHuang, Yi-Leen_US
dc.date.accessioned2012-02-14T22:18:13Zen_US
dc.date.accessioned2012-02-16T16:19:32Z
dc.date.available2012-02-14T22:18:13Zen_US
dc.date.available2012-02-16T16:19:32Z
dc.date.created2010-12en_US
dc.date.issued2012-02-14en_US
dc.date.submittedDecember 2010en_US
dc.identifier.urihttp://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8684en_US
dc.description.abstractGate sizing and threshold voltage (Vt) assignment are very popular and useful techniques in current very large scale integration (VLSI) design flow for timing and power optimization. Lagrangian relaxation (LR) is a common method for handling multi-objectives and proven to reach optimal solution under continuous solution space. However, it is more complex to use Lagrangian relaxation under discrete solution space. The Lagrangian dual problem is non-convex and previously a sub-gradient method was used to solve it. The sub-gradient method is a greedy approach for substituting gradient method in the deepest descent method, and has room for further improvement. In addition, Lagrangian sub-problem cannot be solved directly by mathematical approaches under discrete solution space. Here we propose a new Lagrangian relaxation-based method for simultaneous gate sizing and Vt assignment under discrete solution space. In this work, some new approaches are provided to solve the Lagrangian dual problem considering not only slack but also the relationship between Lagrangian multipliers and circuit timing. We want to solve the Lagrangian dual problem more precisely than did previous methods, such as the sub-gradient method. In addition, a table-lookup method is provided to replace mathematical approaches for solving the Lagrangian sub-problem under discrete size and Vt options. The experimental results show that our method can lead to about 50 percent and 58 percent power reduction subject to the same timing constraints compared with a Lagrangian relaxation method using sub-gradient method and a state-of-the-art previous work. These two methods are implemented by us for comparison. Our method also results in better circuit timing subject to tight timing constraints.en_US
dc.format.mimetypeapplication/pdfen_US
dc.language.isoen_USen_US
dc.subjectVLSIen_US
dc.subjectgate sizingen_US
dc.subjectcircuit optimizationen_US
dc.subjectlow poweren_US
dc.titleAn Improved Lagrangian Relaxation Method for VLSI Combinational Circuit Optimizationen_US
dc.typeThesisen
thesis.degree.departmentElectrical and Computer Engineeringen_US
thesis.degree.disciplineElectrical Engineeringen_US
thesis.degree.grantorTexas A&M Universityen_US
thesis.degree.nameMaster of Scienceen_US
thesis.degree.levelMastersen_US
dc.contributor.committeeMemberWalker, Duncan M.en_US
dc.type.genrethesisen_US
dc.type.materialtexten_US


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