Case Studies on Clock Gating and Local Routign for VLSI Clock Mesh
MetadataShow full item record
The clock is the important synchronizing element in all synchronous digital systems. The difference in the clock arrival time between sink points is called the clock skew. This uncertainty in arrival times will limit operating frequency and might cause functional errors. Various clock routing techniques can be broadly categorized into 'balanced tree' and 'fixed mesh' methods. The skew and delay using the balanced tree method is higher compared to the fixed mesh method. Although fixed mesh inherently uses more wire length, the redundancy created by loops in a mesh structure reduces undesired delay variations. The fixed mesh method uses a single mesh over the entire chip but it is hard to introduce clock gating in a single clock mesh. This thesis deals with the introduction of 'reconfigurability' by using control structures like transmission gates between sub-clock meshes, thus enabling clock gating in clock mesh. By using the optimum value of size for PMOS and NMOS of transmission gate (SZF) and optimum number of transmission gates between sub-clock meshes (NTG) for 4x4 reconfigurable mesh, the average of the maximum skew for all benchmarks is reduced by 18.12 percent compared to clock mesh structure when no transmission gates are used between the sub-clock meshes (reconfigurable mesh with NTG =0). Further, the research deals with a ‘modified zero skew method' to connect synchronous flip-flops or sink points in the circuit to the clock grids of clock mesh. The wire length reduction algorithms can be applied to reduce the wire length used for a local clock distribution network. The modified version of ‘zero skew method’ of local clock routing which is based on Elmore delay balancing aims at minimizing wire length for the given bounded skew of CDN using clock mesh and H-tree. The results of ‘modified zero skew method' (HC_MZSK) show average local wire length reduction of 17.75 percent for all ISPD benchmarks compared to direct connection method. The maximum skew is small for HC_MZSK in most of the test cases compared to other methods of connections like direct connections and modified AHHK. Thus, HC_MZSK for local routing reduces the wire length and maximum skew.
Subjectclock distribution network
clock routing techniques
local routing methods
modified zero skew method
Ramakrishnan, Sundararajan (2010). Case Studies on Clock Gating and Local Routign for VLSI Clock Mesh. Master's thesis, Texas A&M University. Available electronically from
Showing items related by title, author, creator and subject.
Characterizing Novel Circadian Clock Functions for Drosophila Phosphatases and Non-clock Functions for Circadian Photoreceptors Agrawal, Parul (2016-08-03)Circadian (~24 h) clocks regulate daily cycles in gene expression to control overt rhythms in physiology, metabolism and behavior. In Drosophila, a transcriptional feedback loop activated by CLOCK-CYCLE (CLK-CYC) complexes, ...
Peters, Jennifer Lynn (Texas A&M University, 2006-08-16)Melatonin is rhythmically synthesized and released by the pineal gland and, in some species, retina during the night and regulates many physiological and behavioral processes in birds and mammals. Chick diencephalic ...
Kim, Min-seok (Texas A&M University, 2006-08-16)This thesis studies the associative skew clock routing problem, which seeks a clock routing tree such that zero skew is preserved only within identified groups of sinks. Although the number of constraints is reduced, the ...