Countering Aging Effects through Field Gate Sizing
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Transistor aging through negative bias temperature instability (NBTI) has become a major lifetime constraint in VLSI circuits. We propose a technique that uses antifuses to widen PMOS transistors later in a circuit?s life cycle to combat aging. Using HSPICE and 70nm BPTM process numbers, we simulated the technique on four circuits (a ring oscillator, a fan-out four circuit, an ISCAS c432 and c2670). Over the lifetime of the circuit, our simulations predict a 8.89% and a 13% improvement in power in the c432 and c2670 circuits respectively when compared to similarly performing traditional circuits.
SubjectTransistor Ageing Antifuse NBTI negative bias temperature instability FTS Field Transistor Sizing
Henrichson, Trenton D. (2008). Countering Aging Effects through Field Gate Sizing. Master's thesis, Texas A&M University. Available electronically from