A narrow-band high-speed switched-capacitor sixth order bandpass ladder filter

Abstract

In narrow-band high-speed switched-capacitor filters, the main limitation comes from the capacitance spread and from amplifier settling time. A secondary clock, that averages at an integer fraction of the main clock signal, is used to reduce the capacitance spread which reduces power consumption and relaxes amplifier requirements. The secondary clock is pulse position modulated to reduce the power of aliasing distortion. Frequency prewarping equations to account for the secondary clock have been presented. After a review of cascode transconductance amplifiers, a three-path amplifier with reduced input capacitance and enhanced slew-rate has been proposed to improve settling time. The presented amplifiers have been compared with computer simulations. The proposed three-path amplifier has been prototyped in a 0.5[]m CMOS technology and characterized, experimental results have been presented. It achieves a 1% settling time of 3.60ns for a load of 1pF. Finally, a sixth order bandpass ladder switched-capacitor filter with a center frequency of 9.8MHz and main clock frequency of 60MHz has been prototyped in a 0.35[]m CMOS technology. The filter is powered by the proposed three-path amplifiers and uses a secondary clock to reduce the capacitance spread by a factor of four. Experimental results are presented. The filter achieves a bandwidth of 464kHz, a signal-to-noise ratio of 53dB for a power consumption of 54mW and a capacitance spread of 8.