Detection and removal of functional redundancy in multi-level logic circuits
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Whenever digital designs are created, they may contain many logic redundancies. Minimization tools are then used to remove these redundancies. The minimized circuit should be smaller, faster, and cheaper while still behaving like the original circuit. This research will focus on finding non-traditional methods for minimizing multi-level logic circuits.
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Dorsey, David Michael (2002). Detection and removal of functional redundancy in multi-level logic circuits. Texas A&M University. Available electronically from