Timing analysis of digital circuits considering impact of capacitive crosstalk & process variation on path delays

Abstract

Competitive design of modern digital circuits requires high performance at reduced cost and time-to-market. Hence, accurate timing analysis is essential in the design and test of digital integrated circuits. With reduced feature sizes and increasing clock frequency the problem of timing analysis is becoming more and more convoluted and all the more important to decide whether the design under consideration would function correctly at the desired operating frequency when manufactured. In this research, we outline a methodology for timing analysis. We identify the longest paths in the circuit, generate a two-pattern input vector to sensitize those long paths in the circuit and analyze the effect of capacitive crosstalk process variation on the delay of these paths. The methodology outlined here estimates realistic but conservative upper and lower bounds on the delays of the longest paths in the circuit. This timing analysis is done at an abstract level, not considering detailed models for effects of crosstalk and process variations on path delays. Such a detailed analysis is expensive and time-consuming. The delay bounds estimated using this research would help in determining how early in the design flow would a detailed timing analysis be required to identify potential timing violations. We use a path generator that uses an improved dynamic sensitization criterion to identify potential longest paths in the circuit. This path generator also generates a two-pattern input vector to sensitize the long paths in the circuit. Next, we outline a post processing methodology that uses a conservative crosstalk model to model the effect of capacitive crosstalk couplings on the delays of the long paths. We use an iterative approach, where timing iterations are performed on the circuit. Timing iterations are essential to reduce pessimism encountered in the initial estimate of upper and lower bounds on the path delays. Thus, we set realistic but conservative minimum and maximum delay bounds of the path delay. This methodology is tested on the ISCAS'85 benchmark circuits and the timing analysis results obtained are validated using SPICE circuit simulations.