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Practical implementation of a phase locked loop tunable filter less sensitive to process variations
dc.creator | Kripalani, Ayesha | |
dc.date.accessioned | 2012-06-07T22:53:04Z | |
dc.date.available | 2012-06-07T22:53:04Z | |
dc.date.created | 1998 | |
dc.date.issued | 1998 | |
dc.identifier.uri | https://hdl.handle.net/1969.1/ETD-TAMU-1998-THESIS-K75 | |
dc.description | Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to digital@library.tamu.edu, referencing the URI of the item. | en |
dc.description | Includes bibliographical references: p.114-118. | en |
dc.description | Issued also on microfiche from Lange Micrographics. | en |
dc.description.abstract | This thesis describes a strategy for designing manufacturable Integrated Circuits (ICs) using Statistical Circuit Design methods to optimize the performance of circuit design in the presence of uncontrollable variations in the manufacturing process and in the operating conditions. The adopted methodology attempts to optimize a complex system such as a Phase Locked Loop based tunable filter. Once optimized, the system will be compared with the nominal circuit. Finally it will be demonstrated that the optimization methodology adopted produces improved chip performances and reduced variability in accordance to simulations performed prior to its manufacturability. This will result in a system that is robust and less susceptible to variations in the uncertainty of the manufacturing process. In order to achieve the goals of Design for Quality and Manufacturability the following steps were taken: 1.Statistical behavior models developed in Alexander's Thesis [1, 2], were thoroughly analyzed and tested to verify the model appropriateness and accuracy so that they could be practically implemented at the transistor level. 2.The system was designed to meet the specifications used in Alexander's thesis [2]. The performances that were critical and subject to large variations in the process were optimized. 3.Layouts of the optimized system and nominal system were created using [3]; test circuits were designed. The systems were fabricated using MOSIS. The Design for Quality and Manufacturability (DFQM) CAD tools, and other software tools used to implement this research are as follows: 1.GOSSIP[4]: A Generic System for Statistical Improvement of Performance, developed at the Electrical Engineering Department, Texas A&M University. 2.simvis95[5]: A utility program for visualization of statistical optimization data. 3. spectre[6]: Cadence's circuit simulator. 4.artil[6]: Cadence's post-processing tool. 5.HSPICE[7]: HSPICE Circuit Simulator. The application of these tools will be demonstrated in this thesis as the optimization methodology is described. Furthermore, certain assumptions will be made along the way which will be noted and discussed. | en |
dc.format.medium | electronic | en |
dc.format.mimetype | application/pdf | |
dc.language.iso | en_US | |
dc.publisher | Texas A&M University | |
dc.rights | This thesis was part of a retrospective digitization project authorized by the Texas A&M University Libraries in 2008. Copyright remains vested with the author(s). It is the user's responsibility to secure permission from the copyright holder(s) for re-use of the work beyond the provision of Fair Use. | en |
dc.subject | electrical engineering. | en |
dc.subject | Major electrical engineering. | en |
dc.title | Practical implementation of a phase locked loop tunable filter less sensitive to process variations | en |
dc.type | Thesis | en |
thesis.degree.discipline | electrical engineering | en |
thesis.degree.name | M.S. | en |
thesis.degree.level | Masters | en |
dc.type.genre | thesis | en |
dc.type.material | text | en |
dc.format.digitalOrigin | reformatted digital | en |
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