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dc.creatorBalachandran, Hariharanen_US
dc.date.accessioned2012-06-07T22:43:42Z
dc.date.available2012-06-07T22:43:42Z
dc.date.created1996en_US
dc.date.issued1996
dc.identifier.urihttp://hdl.handle.net/1969.1/ETD-TAMU-1996-THESIS-B353en_US
dc.descriptionDue to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to digital@library.tamu.edu, referencing the URI of the item.en_US
dc.descriptionIncludes bibliographical references.en_US
dc.descriptionIssued also on microfiche from Lange Micrographics.en_US
dc.description.abstractFor any semiconductor industry to be competitive, they should be able to meet with the continuous increasing demand in integrated circuits(IC) functionality. Their time-to-market period should also be optimally small. This necessitates the usage of sophisticated processing tools that increases the manufacturing cost. Increasing the manufacturing yield will reduce the effective manufacturing cost per die. Hence integrated circuit manufacturers try to improve yield to profitable levels in a short time frame and to maintain or improve the yields once they are achieved. Yields can be substantially increased when one is able to identify the causes for yield loss, In this research a methodology to identify integrated circuit yield detractors using SRAM functional test results in combination with a defect-bitmap dictionary. We investigate the accuracy of the defect classification under different forms of voltage testing and current testing. In particular we investigate the benefit of using multiple Iddq current levels calibrated to remove normal parametric variations. We also investigate the effects of unmodeled defects and the ability to identify cases of certain and uncertain diagnosis. We have experimentally validated our approach using a production microprocessor cache.en_US
dc.format.mediumelectronicen_US
dc.format.mimetypeapplication/pdfen_US
dc.language.isoen_USen_US
dc.publisherTexas A&M Universityen_US
dc.rightsThis thesis was part of a retrospective digitization project authorized by the Texas A&M University Libraries in 2008. Copyright remains vested with the author(s). It is the user's responsibility to secure permission from the copyright holder(s) for re-use of the work beyond the provision of Fair Use.en_US
dc.subjectelectrical engineering.en_US
dc.subjectMajor electrical engineering.en_US
dc.titleImprovement of SRAM-based failure analysis calibrated IDDQ testingen_US
dc.typeThesisen_US
thesis.degree.disciplineelectrical engineeringen_US
thesis.degree.nameM.S.en_US
thesis.degree.levelMastersen_US
dc.type.genrethesis
dc.type.materialtexten_US
dc.format.digitalOriginreformatted digitalen_US


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