Abstract
In this thesis, a new test algorithm for reprogrammable field programmable gate arrays (FPGAs) is developed. The fault models consisting of stuck-at faults, bridge faults, programmable switch stuck-on, and stuck-off faults, are utilized. Both the logic and interconnection resources are tested by the proposed method in a hierarchical manner. The proposed test method is divided into three parts of several programming steps each. Parts I and II of the proposed method test the interconnection resources. Part III tests the logic resources. Due to the much greater time taken for reprogramming the device (as high as 100 ms for today's FPGAs) the number of test vectors is not of primary concern in the total test time. Hence, the test vectors are not optimized. These test vectors can be easily generated using appropriate configurations in the FPGA. The number of test vectors required is dependent on the number of Logic Elements in the chip. The number of times the chip must be reprogrammed to test the interconnection resources is shown to be 35 for all sizes of Altera FLEX8000 FPGAs. The number of reprogramming steps to test the logic resources is 6 for all sizes of Altera FLEX8000 FPGAs. This yields a total of 41 programming steps. In the largest FLEX8000 FPGA, 80,820 test vectors are required. This takes approximately 0.08s on a I MHz tester. The total test time for the largest FLEX8000 FPGA is approximately 4.18s using the proposed test method. It is shown that the proposed test method is very efficient and detects 100% of single faults, and over 99.999% of multiple faults.
Ashen, David Glen (1996). A comprehensive test method for reprogammable field programmable gate arrays. Master's thesis, Texas A&M University. Available electronically from
https : / /hdl .handle .net /1969 .1 /ETD -TAMU -1996 -THESIS -A844.