Modeling of three dimensional defects in integrated circuits

Abstract

Although the majority of defects found in manufacturing lines of Integrated Circuits [ IC's] have predominantly 2- Dimensional [2D] effects, there are many situations in which 2D defect models do not suffice) e.g., tall layer bulks disrupting the continuity of subsequent layers, abrupt surface topologies, extraneous materials embedded in the IC, etc. In this thesis a procedure to capture the catastrophic effect of 3-Dimensional [3D] defects is presented. This approach is based on the geometrical properties that result from the interaction between the IC and the defect size in two coordinate spaces: x-y and z. The approach is a natural extension to the concept of critical areas, namely, the extraction of critical volumes. Through the course of this work hints to the origins of 3D defects are given, conditions to capture critical volumes are developed and it is shown that the net effect of 3D defects is accumulated from layer to layer. Algorithms are proposed for extracting critical regions from layouts. These regions are displayed on the layouts of benchmark circuits for different defect sizes and defect mechanisms. They have applications in design rule checkers of layout editors, i.e. 7 to optimize layouts for manufacturing conditions. These regions can also be used in creation of accurate yield models. Various layout styles for a particular combinational function are examined to find a most defect tolerant layout. Furthermore , a comparison of the intra and inter layer 3D defects is carried out quantitatively. Sensitivity curves , which show the layout's defect tolerance to certain defect mechanisms are included. Inductive Fault Analysis is performed on a circuit using 2D and 3D single and multiple layer defects. Faults are extracted from a simple layout and and ranked on the basis of their likelihood. Applications of Inductive Fault Analysis towards the testing of IC's are discussed.