| dc.description.abstract | With the relentless shrinking of the minimum feature size of VLSI Integrated
Circuits (ICs), reduction in operating voltages and increase in operating frequencies,
VLSI circuits are becoming more vulnerable to radiation strikes. As a result, this
problem is now important not only for space and military electronics but also for
consumer ICs. Thus, the design of radiation-hardened circuits has received significant
attention in recent times.
This thesis addresses the radiation hardening issue for VLSI ICs. In particular,
circuit techniques are presented to protect against Single Event Transients (SETs).
Radiation hardening has long been an area of research for memories for space and
military ICs. In a memory, the stored state can ip as a result of a radiation strike.
Such bit reversals in case of memories are known as Single Event Upsets (SEUs).
With the feature sizes of VLSI ICs becoming smaller, radiation-induced glitches have
become a source of concern in combinational circuits also. In combinational circuits,
if a glitch due to a radiation event occurs at the time the circuit outputs are being
sampled, it could lead to the propagation of a faulty value. The current or voltage
glitches on the nodes of a combinational circuit are known as SETs. When an SET
occurring on a node of a logic network is propagated through the gates of the network
and is captured by a latch as a logic error, it is transformed to an SEU.
The approach presented in this thesis makes use of Code Word State Preserving
(CWSP) elements at each ip-op of the design, along with additional logic to trigger
a recomputation in case a SET induced error is detected. The combinational part of
the design is left unaltered. The CWSP element provides 100% SET protection for
glitch widths up to min{(Dmin-D1)/2, (Dmax-D2)/2}, where Dmin and Dmax are
the minimum and maximum circuit delay respectively. D1 and D2 are extra delays
associated with the proposed SET protection circuit. The CWSP circuit has two
inputs - the flip flop output signal and the same signal delayed by a quantity 6. In
case an SET error is detected at the end of a clock period i, then the computation is
repeated in clock period i+1, using the correct output value, which was captured by
the CWSP element in the ith clock period. Unlike previous approaches, the CWSP
element is i) in a secondary computational path and ii) the CWSP logic is designed to
minimally impact the critical delay path of the design. It was found through SPICE
simulations that the delay penalty of the proposed approach (averaged over several
designs) is less than 1%. Thus, the proposed technique is applicable for high-speed
designs, where the additional delay associated with the SET protection must be kept
at a minimum. | en |
