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dc.contributor.advisorMercer, M. Ray
dc.creatorWingfield, James
dc.date.accessioned2004-09-30T01:40:20Z
dc.date.available2004-09-30T01:40:20Z
dc.date.created2003-12
dc.date.issued2004-09-30
dc.identifier.urihttp://hdl.handle.net/1969.1/20
dc.description.abstractThis research pursues the use of powerful BDD-based functional circuit analysis to evaluate some approaches to test set generation. Functional representations of the circuit allow the measurement of information about faults that is not directly available through circuit simulation methods, such as probability of random detection and test-space overlap between faults. I have created a software tool that performs experiments to make such measurements and augments existing test generation strategies with this new information. Using this tool, I explored the relationship of fault model difficulty to test set length through fortuitous detection, and I experimented with the application of function-based methods to help reconcile the traditionally opposed goals of making test sets that are both smaller and more effective.en
dc.format.extent261635 bytesen
dc.format.extent67520 bytesen
dc.format.mediumelectronicen
dc.format.mimetypeapplication/pdf
dc.format.mimetypetext/plain
dc.language.isoen_US
dc.publisherTexas A&M University
dc.subjectbinary decision diagramen
dc.subjectBDDen
dc.subjectdigital logic testen
dc.subjecttest generationen
dc.subjectfunction-based test generationen
dc.titleApproaches to test set generation using binary decision diagramsen
dc.typeBooken
dc.typeThesisen
thesis.degree.departmentElectrical Engineeringen
thesis.degree.disciplineComputer Engineeringen
thesis.degree.grantorTexas A&M Universityen
thesis.degree.nameMaster of Scienceen
thesis.degree.levelMastersen
dc.contributor.committeeMemberGrimaila, Michael
dc.contributor.committeeMemberReddy, A. L. Narasimha
dc.type.genreElectronic Thesisen
dc.type.materialtexten
dc.format.digitalOriginborn digitalen


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