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dc.creatorOviedo, Edgar D
dc.date.accessioned2017-10-10T20:28:26Z
dc.date.available2017-10-10T20:28:26Z
dc.date.created2017-05
dc.date.submittedMay 2017
dc.identifier.urihttps://hdl.handle.net/1969.1/164485
dc.description.abstractLiterature Review The structural health monitoring device proposed by Jason Lee Wardlaw in [1] has been shown to have individual circuit blocks that operate at the technology used, which is an ON Semiconductor 0.5µm Complementary Metal Oxide Semiconductor (CMOS) process. To advance this research, an IBM 0.13µm CMOS process will be used to replicate the operability of the circuitry and obtain an overall system integration onto a single semiconductor chip. Thesis Statement The use of the IBM 0.13µm CMOS process will be explored in its ability to replicate the system operability of that proposed in [1]. It will also allow for a higher density of transistors to fit in a single area (allocating less space for each system block to fit on a single chip) and a lowered overall power consumption, making it a suitable sensor for monitoring structural devices that surpass a lifetime comparable to that of civil infrastructures. Theoretical Framework Different CMOS technologies exist in order to build semiconductor chips. TSMC (Taiwan Semiconductor Manufacturing Company), GlobalFoundries, ON Semiconductor, AMS (Austria Mikro Systeme) AG, and AIM (American Institute for Manufacturing) Photonics are among a few of the many companies that supply these technologies. Each of these companies have different CMOS processes; however, for building analog components, not all of them are suitable due to the fact that there are certain transistor properties that need to be manipulated which can only be done at a certain transistor size. For compliance reasons, an IBM (International Business Machines) 0.13µm CMOS process will be used in this research as it is already accessible to the Electrical and Computer Engineering Department at Texas A&M University. Project Description The structural health monitoring device is set to operate under the conditions set forth by the structure being analyzed. The device proposed in [1] places an emphasis on bridges, but similar methods can be applied to any civil structure that exhibits vibrations which can be converted into usable energy. The operating frequency is expected to be around ~20Hz and voltage amplitude acquired by the memory-shape alloy is predicted to be around 1V. Both of these operating conditions were taken into account when building the circuitry that will monitor the health of the civil structure which then set the necessary certain circuit component to build the sensor. This system will contain a component for harvesting vibrational energy, power-conditioning circuitry to supply power to all other blocks of the system, a sensor, a low-power analog-to-digital convertor, and a low-power radio-transmitter to send the data to a central processing location. All system blocks operate under the CMOS process used in [1] but in order to make the system a more robust one, a different technology will be explored which will both reduce the amount of power consumption as well as increase the amount of circuit components which can fit onto a single semiconductor chip. The technology used in research is an IBM 0.13µm CMOS process which greatly reduces the amount of area used by a single transistor and requires less energy to operate in its saturated region. Due to the time constraints of this project, it was only possible to focus on one of the blocks in this system. Although it can be argued that the ADC or the transmitter are vital parts of this sensor, none of the circuity would be functional if a power source were not present, therefore, the extension of this work will devote constructing and optimizing the power harvesting block. In the future, the rest of the blocks will be designed and integrated using the IBM 0.13µm CMOS process as well. After focusing all efforts on the self-powered rectifier, it was found that the same functionality could be obtained from the circuit presented in [1] using a smaller technology. However, some changes are presented in this work that were made in order to optimize the circuit. The details of the changes are presented in the later chapters of this work but in the grand scale, the breakdown voltage of the technology (1.2V) for a single active device was achieved in 3 stages of rectification, the output of the rectifier was shown to have an equivalent output impedance of 17kΩ, and it is possible of supplying a maximum load of around 70µA to external circuitry, which is expected to be enough for the blocks it is supporting.en
dc.format.mimetypeapplication/pdf
dc.subjectSelf-Powered Rectifieren
dc.titleCMOS Integration of a Self-Powered Rectifieren
dc.typeThesisen
thesis.degree.departmentElectrical & Computer Engineeringen
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorUndergraduate Research Scholars Programen
thesis.degree.nameBSen
thesis.degree.levelUndergraduateen
dc.contributor.committeeMemberKarsilayan, Aydin I
dc.type.materialtexten
dc.date.updated2017-10-10T20:28:26Z


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