Equalization Architectures for High Speed ADC-Based Serial I/O Receivers
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The growth in worldwide network traﬃc due to the rise of cloud computing and wireless video consumption has required servers and routers to support increased serial I/O data rates over legacy channels with signiﬁcant frequency-dependent attenuation. For these high-loss channel applications, ADC-based high-speed links are being considered due to their ability to enable powerful digital signal processing (DSP) algorithms for equalization and symbol detection. Relative to mixed-signal equalizers, digital implementations oﬀer robustness to process, voltage and temperature (PVT) variations, are easier to reconﬁgure, and can leverage CMOS technology scaling in a straight-forward manner. Despite these advantages, ADC-based receivers are generally more complex and have higher power consumption relative to mixed-signal receivers. The ensuing digital equalization can also consume a signiﬁcant amount of power which is comparable to the ADC contribution. Novel techniques to reduce complexity and improve power eﬃciency, both for the ADC and the subsequent digital equalization, are necessary. This dissertation presents eﬃcient modeling and implementation approaches for ADC-based serial I/O receivers. A statistical modeling framework is developed, which is able to capture ADC related errors, including quantization noise, INL/DNL errors and time interleaving mismatch errors. A novel 10GS/s hybrid ADC-based receiver, which combines both embedded and digital equalization, is then presented. Leveraging a time-interleaved asynchronous successive approximation ADC architecture, a new structure for 3-tap embedded FFE inside the ADC with low power/area overhead is used. In addition, a dynamically-enabled digital 4-tap FFE + 3-tap DFE equalizer architecture is introduced, which uses reliable symbol detection to achieve remarkable savings in the digital equalization power. Measurement results over several FR4 channels verify the accuracy of the modeling approach and the eﬀectiveness of the proposed receiver. The comparison of the fabricated prototype against state-of-the-art ADC-based receivers shows the ability of the proposed archi-tecture to compensate for the highest loss channel, while achieving the best power eﬃciency among other works.
Analog-To-Digital Converter (ADC)
Bit-Error Rate (BER)
Decision Feedback Equalizer (DFE)
Feed-Forward Equalizer (FFE)
Successive Approximation Register (SAR)
Shafik, Ayman Osama Amin Mohamed (2016). Equalization Architectures for High Speed ADC-Based Serial I/O Receivers. Doctoral dissertation, Texas A & M University. Available electronically from
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