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dc.contributor.advisorWalker, Duncan M.
dc.creatorZhang, Tengteng
dc.date.accessioned2016-04-06T16:00:54Z
dc.date.available2016-04-06T16:00:54Z
dc.date.created2015-12
dc.date.issued2015-12-08
dc.date.submittedDecember 2015
dc.identifier.urihttp://hdl.handle.net/1969.1/156186
dc.description.abstractDelay test is an essential structural manufacturing test used to determine the maximal frequency at which a chip can run without incurring any functional failures. The central unsolved challenge is achieving high delay correlation with the functional test, which is dominated by power supply noise (PSN). Differences in PSN between functional and structural tests can lead to differences in chip operating frequencies of 30% or more. Pseudo functional test (PFT), based on a multiple-cycle clocking scheme, has better PSN correlation with functional test compared with traditional two-cycle at-speed test. However, PFT is vulnerable to under-testing when applied to delay test. This work aims to generate high quality PFT patterns, achieving high PSN correlation with functional test. First, a simulation-based don’t-care filling algorithm, Bit-Flip, is proposed to improve the PSN for PFT. It relies on randomly flipping a group of bits in the test pattern to explore the search space and find patterns that stress the circuits with the worst-case, but close to functional PSN. Experimental results on un-compacted patterns show Bit-Flip is able to improve PSN as much as 38.7% compared with the best random fill. Second, techniques are developed to improve the efficiency of Bit-Flip. A set of partial patterns, which sensitize transitions on critical cells, are pre-computed and later used to guide the selection of bits to flip. Combining random and deterministic flipping, we achieve similar PSN control as Bit-Flip but with much less simulation time. Third, we address the problem of automatic test pattern generation for extracting circuit timing sensitivity to power supply noise during post-silicon validation. A layout-aware path selection algorithm selects long paths to fully span the power delivery network. The selected patterns are intelligently filled to bring the PSN to a desired level. These patterns can be used to understand timing sensitivity in post-silicon validation by repeatedly applying the path delay test while sweeping the PSN experienced by the path from low to high. Finally, the impacts of compression on power supply noise control are studied. Illinois Scan and embedded deterministic test (EDT) patterns are generated. Then Bit-Flip is extended to incorporate the compression constraints and applied to compressible patterns. The experimental results show that EDT lowers the maximal PSN by 24.15% and Illinois Scan lowers it by 2.77% on un-compacted patterns.
dc.format.mimetypeapplication/pdf
dc.language.isoen
dc.subjectPath Delay Test
dc.subjectPower Supply Noise
dc.subjectPost Silicon Validation
dc.subjectTest Compression
dc.titleHigh Quality Test Generation Targeting Power Supply Noise
dc.typeThesis
thesis.degree.departmentComputer Science and Engineering
thesis.degree.disciplineComputer Engineering
thesis.degree.grantorTexas A & M University
thesis.degree.nameDoctor of Philosophy
thesis.degree.levelDoctoral
dc.contributor.committeeMemberShi, Weiping
dc.contributor.committeeMemberLiu, Jyh-Charn
dc.contributor.committeeMemberMahapatra, Rabi
dc.type.materialtext
dc.date.updated2016-04-06T16:00:54Z
local.etdauthor.orcid0000-0002-7929-9708


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