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dc.contributor.advisorPalermo, Samuel
dc.creatorZhian Tabasy, Ehsan
dc.date.accessioned2015-09-21T18:10:48Z
dc.date.available2017-05-01T05:35:44Z
dc.date.created2015-05
dc.date.issued2015-05-12
dc.date.submittedMay 2015
dc.identifier.urihttp://hdl.handle.net/1969.1/155223
dc.description.abstractAs the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well.
dc.format.mimetypeapplication/pdf
dc.language.isoen
dc.subjectAnalog to Digital Converter (ADC)
dc.subjectEmbedded Equalization
dc.subjectADC-Based Receiver
dc.subjectDecision Feedback Equalizer (DFE)
dc.subjectEmbedded Equalization
dc.subjectFeed-Forward Equalizer (FFE)
dc.subjectSerial Link
dc.subjectSuccessive Approximation Register (SAR)
dc.subjectTime Interleaving
dc.subjectWireline
dc.titleDesign of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications
dc.typeThesis
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.disciplineElectrical Engineering
thesis.degree.grantorTexas A & M University
thesis.degree.nameDoctor of Philosophy
thesis.degree.levelDoctoral
dc.contributor.committeeMemberSilva-Martinez, Jose
dc.contributor.committeeMemberPfister, Henry
dc.contributor.committeeMemberKim, Eun
dc.type.materialtext
dc.date.updated2015-09-21T18:10:48Z
local.embargo.terms2017-05-01
local.etdauthor.orcid0000-0002-5040-1932


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