Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications
MetadataShow full item record
As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well.
SubjectAnalog to Digital Converter (ADC)
Decision Feedback Equalizer (DFE)
Feed-Forward Equalizer (FFE)
Successive Approximation Register (SAR)
Zhian Tabasy, Ehsan (2015). Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications. Doctoral dissertation, Texas A & M University. Available electronically from
Showing items related by title, author, creator and subject.
Systematics of 0-Degrees Neutron-Production by 800 Mev Protons on Targets with 27 Less-Than-Or-Equal-to a Less-Than-Or-Equal-to 238 Bonner, BE; Simmons, J. E.; Newsom, C. R.; Riley, P. J.; Glass, G.; Hiebert, John C.; Jain, M.; Northcliffe, L. C. (American Physical Society, 1978)
The bipolar charging of submicrometer particles (0.03 [micrometers is less than or equal to] Dp [is less than or equal to] 0.31 [ micrometers]) by bipolar air ions: an experimental study Laughlin, Gary Jay (Texas A&M University, 1982)Not available
Teamwork Plus Technology Equals Reduced Emissions, Reduced Energy Usage, and Improved Productivity for an Oil Production Facility Booker, G.; Robinson, J. (Energy Systems Laboratory (http://esl.tamu.edu), 2003-05)Suncor Energy Inc. developed a long term plan to expand production from its oil sands operation north of Fort McMurray, Alberta up to 500,000 to 550,000 barrels/day in 2010-2012, while reducing the per barrel energy usage, ...